Electronic circuits and components are prone to damage when subjected to electrostatic discharges, commonly known as ESD. The accumulation of an electrostatic charge can be generated by rubbing insulators together, such as by a person walking, by air currents, etc. The voltage of an electrostatic charge can range from several hundred volts to several thousand volts. When an integrated circuit is subjected to an electrostatic discharge, the voltage and duration is often sufficient to damage semiconductor junctions, thereby rendering circuits unable to function. Capacitors and other components can also be damaged by the voltage of an electrostatic discharge. The current of an electrostatic discharge generally finds a path through the damaged component to a circuit ground or other reference voltage or line.
Because of the potential for damage to electronic circuits by electrostatic discharges, many designs incorporate therein circuits specially designed to short circuit the electrostatic discharge energy to circuit ground and thereby protect the other circuits of the chip or printed circuit board. In practice, the input/output pins of an integrated circuit often include special ESD protection circuits. In addition, the input/output pins of most types of equipment incorporating electronic circuits, such as computers, digital cameras, facsimile machines, printers, etc., provide special ESD protection circuits.
ESD protection circuits may include one or more transistors dedicated to the sensing of ESD voltages and the short circuiting thereof to ground. ESD circuits can also be embodied in discrete components connected between the I/O pins of a circuit board, or the like, and ground. Active components, such as transistors and various types of diodes which clamp the electrostatic voltage to safe levels can be utilized to provide protection against the effects of ESD. ESD protection can be provided by miniature two-terminal devices having a small gap that arcs across when subjected to electrostatic voltages. In addition to a host of other ESD protection devices; a recent emphasis has been placed on the use of voltage materials (VVM) as an ESD protection mechanism. The following patents relate to the use of VVM with integrated circuits to protect the same from the harmful effects of ESD: U.S. Pat. No. 6,693,508 by Whitney et al; U.S. Pat. No. 6,549,114 by Whitney et al; U.S. Pat. No. 6,351,011 by Whitney et al and U.S. Pat. No. 6,211,554 by Whitney.
The voltage variable material can be made using a polymer having finely divided particles dispersed in an organic resin or an insulating medium. The polymeric material consists of conductive particles which are uniformly dispersed throughout the insulating binder. The voltage variable material exhibits a nonlinear resistance characteristic, in that when exposed to low voltages it is highly resistive, and when exposed to electrostatic-type voltage magnitudes, the resistance lowers very quickly. The material also exhibits a very low capacitance, thereby making it compatible for use in protecting high speed digital circuits. Voltage variable materials are disclosed in U.S. Pat. No. 6,191,928 by Rector, et al, the disclosure of which is incorporated herein by reference. Other patents disclosing voltage variable materials include U.S. Pat. Nos. 4,097,834; 4,726,991; 4,997,357; 5,262,754 and 5,955,762.
Attempts have been made to incorporate the voltage variable material into integrated circuits during fabrication of the die. While this technique may be acceptable in terms of the desired end result, it complicates the process by requiring the procedure to be carried out in the clean room environment. In addition, any adverse long term effects of the various polymer materials on the semiconductor material cannot be ascertained to a high degree.
From the foregoing, it can be seen that a need exists to efficiently incorporate ESD protection within a packaged integrated circuit, using voltage variable materials. Another need exists for the use of voltage variable material in conjunction with integrated circuit lead frames, subsequent to the clean room processing stage. Yet another need exists for a technique to integrate VVM in the integrated circuit package subsequent to fabrication of the die, but prior to the encapsulation.